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[Other resource] xsoc-beta-093

Description: This free cpu-ip! use verilog
Platform: | Size: 3341210 | Author: 王军 | Hits:

[Other] jtag_verilog

Description: verilog 实现的jtag ip模块 包括了测试程序-Verilog achieve the JTAG ip modules including test procedures
Platform: | Size: 6047 | Author: 陈俊 | Hits:

[Other resource] ethernet.tar

Description: 以太网10/100M IP核Verilog源码，可综合。-IP Ethernet 10/100 nuclear Verilog source can be integrated.
Platform: | Size: 934772 | Author: 箫勇天 | Hits:

[mpeg mp3] video_compression_systems

Description: 根据jpeg标准用verilog语言编写的视频编码器，此编码器可作为一个通用IP使用，完成数字音频/视频的编解码功能-under jpeg standards with the Verilog language video encoder, this encoder can be used as a common IP use, complete digital audio / video codec
Platform: | Size: 222770 | Author: 崔云飞 | Hits:

[VHDL-FPGA-Verilog] spram

Description: verilog编写的spram，包含顶层模块，控制模块和spram本体，其中spram为Altera提供的ip核，已在quartus 16上运行通过(Verilog written in spram, including the top-level module, control module and spram ontology, where spram is the IP kernel provided by Altera, has been running on quartus 16)
Platform: | Size: 2857984 | Author: keykai | Hits:

[Other] FFT v1

Description: IP core fft verilog code example
Platform: | Size: 5766144 | Author: mrv | Hits:

[VHDL-FPGA-Verilog] 06_pll_test

Description: 锁相环IP核的使用，包括详细的配置，适合学习使用；(The use of PLL IP core, including detailed configuration, suitable for learning to use;)
Platform: | Size: 232448 | Author: 声声不洗 | Hits:

[VHDL-FPGA-Verilog] 10_rom_test

Description: rom ip核的配置，以及测试文件，适合初学者使用。(ROM IP core configuration, as well as test files, suitable for beginners to use.)
Platform: | Size: 4237312 | Author: 声声不洗 | Hits:

[VHDL-FPGA-Verilog] parallel_norflash_test

Description: ISE工程，并行nor flash的读、写、擦出，其中有个调用FIFO16-16的IP核，已经在工程中(ISE engineering, parallel nor FLASH read, write, erase, where there is a call FIFO16-16 IP core, has been in the project)
Platform: | Size: 1124352 | Author: 张超 | Hits:

[VHDL-FPGA-Verilog] AMBA_VIP

Description: AMBA 总线IP 核Verilog代码(AMBA bus IP Verilog code)
Platform: | Size: 79872 | Author: 逐末 | Hits:

[VHDL-FPGA-Verilog] Module基础全集

Description: 如题，各种veirlog 基础代码大全，虽功能不及ip核，但却可以学习到很多(For example, all kinds of veirlog base code, though not as functional as IP core, can learn a lot)
Platform: | Size: 32768 | Author: halibote | Hits:

[VHDL-FPGA-Verilog] rtl

Description: 基于S10新品的2x2矩阵乘模块，附带双精度的乘法，除法ip核(2x2 matrix multiplication module based on S10 new product, with double precision multiplication, division IP kernel)
Platform: | Size: 590848 | Author: Rdddd | Hits:

[Communication-Mobile] 14_ethernet

Description: 使用verilog语言实现了udp发送 接收(Implementation of UDP sending and receiving)
Platform: | Size: 9023488 | Author: zhao1234 | Hits:

[VHDL-FPGA-Verilog] iir_2n_ip_float_demo

Description: 使用altera提供的ip核，实现了浮点数运算的2阶iir滤波器，结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)
Platform: | Size: 48926720 | Author: 小天夫斯基 | Hits:

[VHDL-FPGA-Verilog] at7_ex04

Description: 通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)
Platform: | Size: 1833984 | Author: 24fh | Hits:

[VHDL-FPGA-Verilog] FIR设计实现sgh

Description: FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
Platform: | Size: 25600 | Author: 韩冻少 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: 本次的设计主要任务是学会调用锁相环 IP 核，并对其进行仿真， 具体要求如下：（1）熟练掌握调用锁相环 IP 核的详细步骤。将 50M 的时钟分成 20MHz 和 100MHz 两个时钟（2）对锁相环进行仿真，验证 调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)
Platform: | Size: 218112 | Author: 小猪仔521 | Hits:

[VHDL-FPGA-Verilog] tcp_ip_core_w_dhcp_latest.tar

Description: 以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)
Platform: | Size: 152576 | Author: 翾飞FEI | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

[Embeded-SCM Develop] cordic

Description: 该程序实现了Cordic算法，未调用IP核通过Cordic算法进行三角函数运算(This program implements Cordic algorithm and does trigonometric function operation through Cordic algorithm without calling IP core.)
Platform: | Size: 2704384 | Author: 小明d1 | Hits:
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